1. Field of the Invention
The present invention relates to a phase-frequency detector which detects a frequency error between two signals from a temporal change in a phase error signal representing the phase difference between the two signals corrects the phase error signal, and outputs the corrected phase error signal, and a phase-locked loop circuit incorporating the phase-frequency detector.
2. Description of the Related Art
A phase-locked loop (PLL) circuit is used to recover a carrier from an intermediate frequency (IF) signal. In this case a baseband signal consisting of an I-phase signal and a Q-phase signal is generated by multiplying the input IF signal by two recovered quadrature carriers. These component signals are converted by A/D converters into digital signals and the values of the I-phase and Q-phase signals are fed as addresses to a ROM where the value of tan.sup.-1 (Q/I) is stored, to generate the phase error signal related to the phase difference between the input signal and the recovered carrier. The frequency of the recovered carrier is controlled by the phase error signal thus generated and whose high-frequency component has been removed by a low-pass filter.
The phase error signal generated as described above varies periodically within the range of .+-.180.degree. because of the periodicity of the function tan.sup.-1. Accordingly, if the frequency of the input signal is far from that of the recovered carrier there arises the problem that synchronization cannot be established or the time required to establish synchronization becomes extremely long.